The present application relates to semiconductor manufacturing. More particularly, the present application relates to an interposer that includes a non-silicon interposer substrate having a lattice framework and a plurality of unit cells formed therein. Each unit cell includes a plurality of conductive metal structures embedded in, and laterally surrounded by, a dielectric material.
To improve the level of integration and connectivity between semiconductor wafers, various stacking technologies have been proposed to increase the functionality by aggregating discrete components at very fine interconnect pitches onto a single planar carrier or interposer. Silicon has been the material of choice for prior interposers because there is a known supply chain, process tooling set and knowledge base for creating high density interconnects on silicon. Silicon as an interposer however has drawbacks. For example, the semiconductor behavior of silicon requires electrical isolation at all conductor interfaces. Also, silicon has a fixed thermal coefficient of expansion (TCE) of about 2.6 ppm/° C. that limits the maximum cross-sectional area of conductive filled vias in thermal cycling/reliability tests and subsequent BA operations to common laminates (with TCEs of approximately 10-12 ppm/° C.), again with reliability implications.
Glass interposers have been touted as a replacement for silicon interposers due to their better electrical resistance and availability of higher TCEs. One major problem with glass is the immature processes for creating holes in the 10-30 μm range. Lasers, machining, electrochemical machining, wet etching, which have traditionally be employed to create holes into glass, all have issues with either minimum feature size or throughput in the hours/days at via densities of interest which drive very expensive and/or high tooling unit purchase. A need therefore exists for providing a simple and cost efficient method for creating glass interposers with small holes (30 μm or below). In particular this need is highlighted for large panel size starting materials to facilitate economy of scale cost reductions vs. 300 mm diameter current limitations in wafer processing tools and platforms.